用于零延迟缓冲器的PLL设计

Design of PLL for zero delay clock buffer

本文设计了一款用于零延迟时钟缓冲器的PLL,采用一种结构简单并且实现低失配的电荷泵,详细阐述了对噪声有很强抑制作用的一种差分结构的压控振荡器,采用CSMC0.5μmN阱CMOS工艺,在3.3V电源电压下,该PLL的工作频率范围为10MHz-140MHz,周对周抖动为45ps@50MHz,功耗为4.8mW,芯片面积为1.2μm×1.7μm。

A PLL applied in zero delay clock buffer has been designed using CSMC 0.6um N-well CMOS process.This paper presents a charge pump with simple structure and which achieves low current dismatcb.And a differential voltage controlled oscillator （VCO） with high noise rejection is described in detail.At 3.3V voltage supply ,the proposed PLL operates in the range of 10MHz to 140MHz. Its cycle-cycle jitter is 45ps@50MHz with 4.8mV power consumpion .The die area is 1.2μm×1.7μm.