摘要
介绍了一种专用集成电路芯片性能测试系统的设计与实现,该芯片适用于构建硅探测器前端读出电子学。描述了测试系统主要硬件电路设计,基于CPLD的快读出控制时序发生模块的实现,利用并口线来模拟I2C总线的方法,系统的调试和主要性能的分析。
A test system for front-end ASIC chip that developed for optimum performance with silicon strip detector was presented in this paper. The main circuit, implementation of a fast read-out control pulse generator based on CPLD and the realization of I^2C bus using lines in parallel port were introduced. And the debugging and the performance analysis of the testing system were described.
出处
《核技术》
CAS
CSCD
北大核心
2009年第9期701-705,共5页
Nuclear Techniques
基金
国家自然科学基金资助(10675153)项目
