组合电路测试生成的PODEM算法及实现

Podem Algorithm and its Realization on Combined Logic Circuits

详细讨论了在已知组合电路结构，对多输入器件，根据组合电路的等效性，附加虚拟器件，将电路的树形数据结构化为二叉树结构，采用ＰＯＤＥＭ算法，按最难／最易原则回溯，在计算机上实现电路中的单一恒定故障（Ｓ－ａ－０和Ｓ－ａ－１）的测试矢量生成。

This paper discusses,with the combined logic circuits and the circuits' equivalent principle taken into consideration,how the circuits data tree is turned into one with binary branches by using additional virtual circuits for increasing the research speed.According to the single stuck and by using the Podem algorithm,the minimal test set of fault models S a 0 (stuck at 0) and S a 1 (stuck at 1) in the circuits is realized.And an example of verification is also discussed in this paper.