VHDL综合系统HLS/BIT中永真式的判定算法

A Fast Algorithm for Judging Tautology in VHDL Synthesis System HLS/BIT

在ＥＤＡ设计工具的ＨＤＬ综合系统中，高级综合、ＲＴＬ级综合和逻辑级综合等都常常需要对逻辑函数进行永真式的判定。本文给出一种高效的永真式判定算法，该算法利用余因子、Ｓｈａｎｎｏｎ展开式和单边函数，对逻辑函数的多维体列阵进行快速有效的递归判定。该算法已经在自行研制的ＶＨＤＬ综合系统ＨＬＳ／ＢＩＴ中实际应用。

In HDL synthesis systems of EDA design tools, it often needs to be judged in high-level synthesis, RTL-level synthesis and logic-level synthesis whether a logical function is a tautology. This paper gives a fast algorithm based on the concepts of cofactor, Shannon expansion and unate function to recursively and quickly judge if a given cube array of logical function is a tautology. This algorithm has been used in the VHDL synthesis system HLS/BIT.