低相噪、低杂波数字锁相环路滤波器的设计

Low Phase Noise and Spurious Digit PLL′s Loop Filter Design

较详细地分析数字锁相频率合成器的相位噪声，着重用控制论方法对低相噪、低杂波锁相环的环路滤波器进行设计，并用某Ｓ波段频率合成器的实验结果进行了验证。

This paper analyzes phase noise of digit PLL frequency synthesizer in detail, emphasises design of low phase and spurious PLL′s loop filter with control theory, and the viewpoint has been testified with results of S band synthesizer.