基于FPGA的AES-128加密芯片的设计与实现

The Design and Implementation of AES-128 Algorithm Based on FPGA

介绍了基于Altera公司的系列FPGA的AES-128加密算法的具体实现方案,优化了字节替换,设计了简化结构的列混合/逆列混合变换,最终实现了加解密模块的复用,从而有效减少了硬件资源的消耗。通过在芯片EP1C12Q240C8上的验证,在100MHz工作频率下,数据吞吐率达到256Mbps,而芯片规模不超过30K门。试验表明该方案能够以较少的资源获得较高的吞吐率。

This paper introduces the specific implementation of AES-128 Algorithm based on Cyclone II FPGA. Through the optimized design of SubBytes, and the simplified structure of MixColunms/InvMixColumns, this system achieves reusable design for the encryption and decryption modules, and then it reduces the area cost effectively. The verification on FPGA shows this design can achieve the better throughput, and the throughput can be up to 256Mbps, under the working frequency at 100MHz, while the chip scale is less than 30K gates.