用于ADC的高速高增益全差分运算放大器设计

Design for High-speed and High-gain Fully Differential Operational Amplifier Based on ADC

针对Sigma-Delta ADC中全差分共模反馈运算放大器的要求,设计了一种高速、高增益、宽输出摆幅的运算放大器.采用HJTC 0.35 m CMOS工艺,使用Hspice对电路进行了仿真分析.结果表明,在电源电压为3.3 V时,运算放大器低频增益为100 dB、相位裕度为72度、单位增益带宽为68MHz.

Based on Sigma-Delta ADC fully differential common mode feedback operational amplifier （op-amp）, an op-amp with high speed, high voltage gain and wide output swing was designed. The schematic simulation was implemented by the tools of Hspice with HJTC 0.35 m CMOS technology. The simulation results show that low-frequency op-amp gain is 100 dB, phase margin is 72 degrees, unit gain bandwidth is 58 MHz at the power supply voltage of 3.3 V.