基于FPGA的图像中值滤波算法的优化及实现

针对FPGA可并行流水线工作的结构特点,对图像中值滤波算法进行了优化,并用VHDL语言在altera公司的现场可编程门阵列上进行了实现,并给出了部分关键程序。实验结果证明,该算法可满足实时性要求,滤波效果良好,适用于图像采集和预处理系统中。

Image median filter algorithm is optimized according to the characters of FPGA. The algorithm is executed in the FPGA of Altera using VHDL, and part of key program is given in the paper. The experimental results show that the optimized method is applicable for real-time median filtering and image acquisition and pre-processing system.