VLSI的电镀和化学机械抛光技术

Electroplate and chemical mechanical polishing technology of ULSI

从0.13μm工艺节点开始,铜电镀(ECP)和化学机械抛光技术(CMP)成为VLSI(超大规模集成电路)多层铜互连布线制备中不可缺少的工艺。铜CMP后的碟型、侵蚀等平坦性缺陷将使芯片表面厚度不均匀,形成互连RC延迟,影响芯片性能和良率;研究发现,铜CMP后的厚度变异不只受CMP影响,还受ECP后芯片厚度影响;文章介绍了ECP、CMP对铜CMP后厚度影响的实验研究,针对CMP后厚度不均匀性的解决方法,着重分析了基于可制造性设计的电镀和化学机械抛光技术,如基于设计规则、电镀和化学机械抛光模型的金属填充等。

In sub-130 nm technology nodes, electro-copper plating（ECP） and chemical mechanical pol- ishing（CMP） after ECP have gained broad applications in the copper interconnect process. The surface defects such as dishing and erosion after copper CMP make the chip surface thickness non-uniform,which leads to the RC delay and then reduces the performance and yield of chips. The study finds that the post-CMP thickness range is not only influenced by CMP, but it is also affected by the post-ECP thickness range. In this paper, the experimental investigations of the influence of ECP and CMP on the post-CMP thickness range are introduced, the current solutions for post-CMP thickness non-uniformity are presented, and the DFM-based ECP and CMP technology is discussed in detail, such as rule-based dummy filling, ECP and CMP model-based dummy filling.