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Thermal characteristics investigation of high voltage grounded gate-LDMOS under ESD stress conditions

Thermal characteristics investigation of high voltage grounded gate-LDMOS under ESD stress conditions
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摘要 The thermal characteristics of high voltage gg-LDMOS under ESD stress conditions are investigated in detail based on the Sentaurus process and device simulators.The total heat and lattice temperature distributions along the Si–SiO2 interface under different stress conditions are presented and the physical mechanisms are discussed in detail.The influence of structure parameters on peak lattice temperature is also discussed,which is useful for designers to optimize the parameters of LDMSO for better ESD performance. The thermal characteristics of high voltage gg-LDMOS under ESD stress conditions are investigated in detail based on the Sentaurus process and device simulators.The total heat and lattice temperature distributions along the Si–SiO2 interface under different stress conditions are presented and the physical mechanisms are discussed in detail.The influence of structure parameters on peak lattice temperature is also discussed,which is useful for designers to optimize the parameters of LDMSO for better ESD performance.
作者 孙伟锋 钱钦松 王雯 易扬波
机构地区 National ASIC System Engineering Research Center
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2009年第10期43-45,共3页 半导体学报（英文版）
基金 supported by the Natural Science Foundation of the Jiangsu Province(No.BK2008287) the Advanced Research of National Natural Science Foundation of Southeast University(No.XJ2008312)
关键词 thermal characteristic gg-LDMOS ESD stress condition thermal characteristic gg-LDMOS ESD stress condition
分类号 TN386.1 [电子电信—物理电子学]
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参考文献7

  • 1Murari B, Bertotti F, Vignola G A. Smart power IC's. Berlin: Springer, 1996.
  • 2Sun Weifeng, Shi Longxing, Sun Zhilin, et al. High voltage power integrated circuit technology with N-VDMOS, RESURF P-LDMOS and novel level shift circuit for PDP scan driver IC. IEEE Trans Electron Devices, 2006, 4:891.
  • 3Vinson J, Liou J J. Electrostatic discharge in semiconductor devices: an overview. IEEE Proc 1998, 86:399.
  • 4Duvvury C, Amerasekera A. ESD: a pervasive reliability concern for IC technologies. IEEE Proc, 1993, 81 : 690.
  • 5Mergens M, Wilkening W, Mettler S, et al. Analysis and compact modeling of lateral DMOS power devices under ESD stress conditions. Electrical Overstress/Electrostatic Discharge Symposium Proceedings, Orlando, FL, USA, 1999:1.
  • 6Boselli G, Meeuwse S, Mouthaan T, et al. Investigations on double-diffused MOS transistors under ESD zap conditions. Microelectronics Reliability, 2001, 41:395.
  • 7Walker A J, Ward S T, Puchner H. Novel robust high voltage ESD clamps for LDMOS protection. IEEE 45th Annual International Reliability Physics Symposium, Phoenix, 2007:596.
Journal of Semiconductors
2009年 第10期

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