H.264视频解码IP核的设计与实现

Design and application of H.264 IP core

设计了一种基于FPGA高效并行结构的H.264视频解码IP核,提出了优化遍历查表的CAVLC熵解码设计方案,并详细介绍了全流水线并行运算结构的反量化反DCT变换模块和帧内预测模块的硬件实现。设计通过Altera公司Stratix Ⅱ系列的EP2S60F672C5ES平台验证,在最高时钟频率82 MHz下能以50 f/s的速度解码分辨率为320×240的灰度图像,在速度、功耗、成本、可移植性等方面都具有独特的优势和良好的发展空间。

This paper describes the design of a highly parallel structure H.264 IP core based on FPGA. At the design stage, we propose an optimized method of CAVLC table＇s looking up. The hardware application of entire pipeline parallel arithmetic inverse quantization, inverse DCT module and intra prediction module is also introduced in detail. The H.264 coding system is tested on the EP2S60F672CSES. At the highest clock frequency of 82 MI-Iz, it can process 50 gray images with the resolution of 320x240 in a second, which has unique advantage and good space for development in speed, power consumption, cost, portability and so on.