OPB总线仲裁器的RTL设计与FPGA实现

The RTL design and FPGA implementation of OPB arbiter device

本文详细介绍了OPB总线仲裁器的信号和仲裁机理。在QuartusII8.0平台上,分别用固定优先级算法和LRU算法,用硬件描述语言(verilogHDL)对OPB总线仲裁器进行了RTL硬件建模。并用FPGA进行实现,并比较了仿真结果和综合结果,两种算法都通过了RTL和网表之间的形式验证。

This paper introduces the signals and mechanism of OPB arbiter in detail. On the QuartusⅡ8.0 platform ,the arbiter is implemented in verilog HDL rtl level based on fixed priority algorithm and LRU algorithm. After synthesis with FPGA, we compare the two algorithm＇s simulation and synthesis result. The formal verification report is also given.