基于SystemVerilog的验证平台建模技术

Modeling Technology of Verification Platform Based on SystemVerilog

验证平台建模的困难在于如何减少设计与验证之间的时序竞争风险,实现验证平台的复用和验证过程中的自动监测。SystemVerilog突破了验证平台建模的传统局限,能够极大地提高芯片测试的效率,并降低设计风险。介绍了SystemVerilog在进行同步FIFO验证平台建模时所采用的面向对象思想、多线程、接口、邮箱、时钟块等新技术以及建立验证平台的一般原则和技巧,实现了分层设计和验证过程中的自动监测。

Difficulty in modeling FIFO verification platform is how to reduce the timing race risks between design and verification,and how to reuse the platform and automatic monitor of the verification process.SystemVerilog breakthrough the traditional limits in modeling verification platform.It can promote the efficiency of testing chips extremely and reduce the design risks.The thought of Object Oriented Programming（OOP） in modeling FIFO verification platform and the new technologies such as multiple threads, interface, mailbox, clocking block and the general principles, skills in modeling verification platform are introduced. Hierarchical design and automatic monitoring are realized.