摘要
采用非易失性逻辑电路与非易失性嵌入式存储器即可实现具有零待机功耗的芯片。目前有很多芯片都采用了具有非易失性的嵌入式存储器,但如果能够令用于临时保存计算结果的触发器(寄存器)具有非易失性,那么,在先断电然后又重新上电时,逻辑电路就仍可继续正常工作。由于芯片上的模拟电路与电源电路等均无需保存数据,所以在待机模式下可以完全关断整个芯片的所有电源,从而实现零待机功耗。目前有两种实现非易失性触发器的方案,包括基于FRAM的方法和基于MRAM的方法。
Imagine a chip that waits in OFF mode for an input,instantly turning on the power for processing when an input is detected,and then turns itself off again.An IC technology that might make possible this type of'normally-off'equipment will enter practical use in 2009:zero standby dissipation chips,achieved by making the entire chip,including logic,nonvolatile.As environment-friendly equipment becomes ever more important,this may be the trump card in slashing power consumption.
出处
《电子设计应用》
2009年第7期30-33,共4页
Electronic Design & Application World
