期刊文献+

透过专利看微处理器的技术发展(九)——多核处理器中Cache专利技术分析

Technology Development of Microprocessor from Patents(IX)——Technology Development on Patent of CMPs Cache
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摘要 本文在对近几年多核处理器中高速缓存(Cache)相关专利进行深入全面的调查基础上,以Intel公司的专利为样本,分析了微处理器进入多核时代后Cache技术研究重点。对多核中Cache关键技术的发展趋势进行了展望,希望能为产品研发提供线索和思路。 In this paper, we made an in-depth analysis about patents of CMPs ( Chip Multi Processors ) Cache. Based on a thoroughly research of relevant patents, we take patents from INTEL as samples, and places great emphasis on the key technology of Cache on CMPs. The future trends of such reach fields are discussed in the end, and we hope our work can provide some reference and enlightens
出处 《中国集成电路》 2009年第9期82-88,共7页 China lntegrated Circuit
关键词 专利文献 多核 高速缓存 一致性 共享高速缓存 Patents CMPs ( Chip Multi Processors ) Cache coherency shared cache
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参考文献4

  • 1何军,王飙.多核处理器的结构设计研究[J].计算机工程,2007,33(16):208-210. 被引量:24
  • 2多核处理器中CACHE一致性协议研究和实现.
  • 3C. Kim, D. Burger, and S. Keckler, "Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches," IEEE MICRO, vol. 272, pp. 03, 2003.
  • 4M. R. Marty, "Cache coherence techniques for multicore processors," University of Wisconsin at Madison, 2008, p. 205.

二级参考文献8

  • 1Kunle O K,Basem A N,Hammond L,et al.The Case for a Single-chip Multiprocessor[C]//Proc.of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems,New York.1996-10-02.
  • 2Tullsen D M,Eggers S J,Levy H M.Simultaneous Multithreading:Maximizing On-chip Parallelism[C]//Proc.of the 22nd Ann.Int'l Symp.on Computer Architecture.1995:392-403.
  • 3Kahle J A.Introduction to the Cell Multiprocessor[J].IBM Journal Res.& Dev.,2005,49(4/5):589-604.
  • 4Kongetira P.A 32-Way Multithreaded SPARC Processor[J].IEEE Micro,2005,25(2):21-29.
  • 5Barroso L A.Piranha:a Scalable Architecture Based on Single-chip Multiprocessing[C]//Proc.of Int'l Symp.on Computer Architecture.2000:165-175.
  • 6Kalla R.IBM Power5 Chip:A Dual-core Multithreaded Processor[J].IEEE Micro,2004,24(2):40-47.
  • 7McNairy C,Bhatia R.Montecito:A Dual-core,Dual-thread Itanium Processor[J].IEEE Micro,2005,25(2):10-20.
  • 8Hammond L.The Stanford Hydra CMP[J].IEEE Micro,2000,20(2):71-84.

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