CMOS数字电路功耗分析及其应用

Power Estimation of CMOS Digital Circuits and Its Application in Low Power Logic Synthesis

讨论了有关ＣＭＯＳ数字电路的功耗分析和低功耗逻辑综合的一些方法。研究了信号的翻转概率与信号概率之间的关系，并由此得到信号翻转次数的表达式。然后讨论了使平均功耗最优的组合逻辑电路优化中的一些方法。最后，提出了两个用于低功耗逻辑综合的基本定理。

Some bassic issues regarding the estimation of power dissipation and techniques for logic synthesis of low power CMOS digital circuits are examined.The expression of the number of signal transitions as a function of the number of applied input vectors and input signal probabilities is derived.Some techniques used in the synthesis of combinational circuits,where the objective is to minimize the average power dissipation,are discussed.Finally,two theorems for low power logic synthesis are presented.