MPEG-1系统解码电路的一种VLSI结构

A VLSI Structure of MPEG 1 System Demultiplexer

根据ＭＰＥＧ－１系统流的特点，用有限状态机的方案设计出ＭＰＥＧ系统解码电路的ＶＬＳＩ结构。该结构具有数据处理速度快和芯片面积小的特点。同时，状态优化和抗错能力强，有较强的实用性。

Based on the characteristics of MPEG 1 system stream,a VLSI structure of MPEG system demultiplexer is designed using the finite state machine.With this structure,it is easy to achieve high data process speed and small chip area.It also features the optimization of state distribution and robustness in error prone environments.