高抗电源噪声的低时钟抖动VCO设计

Design of Low-Clock Jitter VCO with Strong Ability of Rejecting Power Supply Noise

设计了一种基于电流舵逻辑(CSL)架构的环型压控振荡器(VCO),对传统的共源共栅结构偏置电路作了进一步的改善,增加了一个电压增益较大的放大器构成有源负反馈,以提高抗电源噪声的能力.采用和舰0.18μm双阱CMOS工艺对传统结构VCO和改进后的VCO进行对比仿真,在频率为20MHz、峰-峰值为200mV的高频电源噪声下,传统结构VCO的峰-峰抖动和均方根抖动分别为54.135 ps和19.454 ps,而改进结构VCO的相应值分别为27.442 ps和9.196 ps,抗抖动性能大大提高.改进结构VCO的输出频率为650MHz,占空比约为52%,中心控制电压0.9V对应的增益为962.16MHz/V,线性度良好,在1.8V的直流电源下功耗仅为0.7mW左右.

A kind of ring voltage-controlled oscillator（VCO） based on the current steering logic is designed,and the conventional cascode bias circuit is improved by introducing a amplifier with large voltage gain to constitute a new active negative feedback structure with strong ability of rejecting power supply noise.Then,a contrast simulation of the conventional VCO and the improved one is conducted with HEJIAN 0.18μm twin-well CMOS technology.The results indicate that the peak-peak jitter and the RMS（Root Mean Square） jitter of the conventional VCO are respectively 54. 135 ps and 19. 454 ps under the high-frequency power supply noise with a frequency of 20 MHz and a peak-peak amplitude of 0. 2 V, while the corresponding values of the improved VCO are respectively 27. 442 ps and 9. 196 ps, which reveals better jitter performance of the improved VCO. Moreover, the improved VCO is of an output frequency of650MHz, a duty cycle of about 52%, a voltage gain of 962. 16 MHz/V for a central control voltage of 0. 9 V with good linearity, and a low power dissipation of only about 0. 7 mW in 1.8 V DC power supply.