利用FPGA实现数字锁相及频率转换

The Implementation for DPLL and Frequency Translation with FPGA Devices

介绍了用ＦＰＧＡ（现场可编程门阵列）器件实现数字锁相环路和频率转换功能，分析了数字锁相环路的基本原理及实现过程，对设计实现过程中应注意的相关问题也作了具体讨论。

An implementation of the functions, digital phase locked loop (DPLL) and frequency translation, with FPGA (Field Programmable Gate Array) is presented in this paper. The working principle and developing process of DPLL are analyzed and the problems in some aspects concerned in their design and implementation are also discussed.