13bit 50MS/s CMOS流水线ADC的设计

Design of a 13 bit 50 MS/s CMOS Pipelined ADC

介绍了一种新的流水线ADC校准算法,并利用该校准算法完成了一个13 bit,50MS/s流水线ADC的设计。该校准算法对级电路的比较器和后级电路的输出码字的出现频率进行统计,得到各个级电路输出位的真实权值,可以同时校准多种非理想因素如运放有限增益、电容失配等造成的误差。电路采用UMC0.18μm混合工艺,1.8V电源电压。通过SPECTRE仿真获得晶体管级级电路的输入输出关系,将其结果导入顶层行为级模型进行校准。仿真结果表明,在50MHz采样率、5MHz输入信号下,通过校准算法SFDR由44.1dB提升至102.2dB,SNDR由40.9dB提升至79.9dB,ENOB由6.5bit提升至12.98bit。

A new digital background calibration technique was presented for pipelined ADC, and the design scheme of a 13 bit 50 MS/s pipelined ADC was designed with the proposed calibration technique. The real weight of each digital bit can be recalculated by making statistics of occurrence frequency of the output codes from comparator and backend ADC. Multiple errors from different error sources, such as finite Opamp gain and capacitor mismatch can be calibrated with the recalculated real weight. The circuit design was implemented in UMC 0.18 μm mixed mode CMOS technology with 1.8 V supply voltage. The input-output relationship of each transistor level stage circuit was got by SPECTRE simulation, and was calibrated in the top-level behavior model. Simulation results show with 50 MHz sampling rate and 5 MHz input signal, the proposed calibration technique increases SFDR from 44.1 dB to 102.2 dB, SNDR from 40.9 dB to 79. 9 dB and ENOB from 6.5 bit to 12.98 bit.