基于FPGA的扩频接收机中数字匹配滤波器的设计

Design of Digital Matched Filter Based on FPGA in Spread Spectrum Receiver

本文在分析匹配滤波器的工作原理及制约数字匹配滤波器性能的主要参数后,在文献[5]所给出折叠匹配滤波器的基础上设计了一种改进的折叠匹配滤波器结构,该结构具有更好的可实现性和更少的FPGA资源消耗。该设计已经应用于某型号中频数字化直接序列扩频接收机中,并取得了满意的效果。

Through analyzing operation principle of matched filter and the key parameters which constrain performance of digital matched filter （ DMF）, an improved folded matched filter architecture is designed on the basis of a folded matched filter provided in reference [ 5 ]. It is more realizable and consumes less FPGA resource, and it has behaved well in some digital intermediate frequency （IF） direct sequence spread spectrum （DSSS） receiver.