H.264/AVC中并行通用变换结构设计(英文)

Parallel Multi-Transform Architecture Design for H.264/AVC

提出了一种用于H.264/AVC编解码器的通用并行变换结构,并利用Verilog语言进行了电路设计。该并行结构主要包含4个移位器和16个累加器,可以完成H.264/AVC中的全部4×4变换,包括4×4哈达马变换和4×4离散余弦变换和反变换,能够达到每个时钟周期处理一个像素点的速度。使用SMIC0.18μm工艺对该并行结构进行了综合,电路面积为3757门,工作在100MHz时钟频率下的关键路径为10.3ns.

A multi-transform architecture and the Verilog design for all the integer transforms used in H.264/AVC codecs is presented.Consisting of four shifts and 16 accumulators,the parallel multi-transform architecture can perform 4×4 Hadamard transform,4×4 forward discrete cosine transform（FDCT）and 4×4 inverse discrete cosine transform（IDCT）,beable to process one pixel per clock.The hardware architecture is synthesized with SMIC 0.18 μm technology.Results show that the total area is 3757 gates and the critical path is 10. 3 ns working at 100 MHz clock frequency.