基于DSP Builder的16阶FIR滤波器实现

Design of 16-taps FIR Filter Based on DSP Builder

现场可编程门阵列(FPGA)器件广泛用于数字信号处理领域,而使用VHDL或VerilogHDL语言进行设计的难度较大。提出一种采用DSP Builder实现FIR滤波器的设计方案,按照Matlab/Simulink/DSP Builder/Modelsim/QuartusⅡ的设计流程,设计一个16阶的FIR低通滤波器,并完成了软硬件的仿真与验证。结果表明,该方法简单易行,可满足设计要求,它验证了采用DSP Builder实现滤波器设计的独特优势。

Field Programmable Gate Array（FPGA）devices is widely used in the field of digital signal processing,it is difficult to design using VHDL or VerilogHDL. A model development technology of DSP Builder is adopted to design FIR filter, according to the flow of Matlab/Simulink/DSP Builder/Modelsim/Quartus Ⅱ , a 16 - taps low - pass FIR filter is designed, which is simulated and verified in the digital signal process circuit,the results show that the method is simple,feasible and the advantage of designing digital filter by the use of DSP builder are verified.