基于DDS和PLL的宽带时钟发生电路设计

A Wideband and Variable Clock Generator Based On Direct Digital Synthesis and Phase Locked Loop

针对高速任意波形发生器对高精度、宽带时钟电路的需要，提出了一种通过DDS加PLL的可变时钟设计方法。对DDS参数的选择、锁相环倍数的选择进行了详细分析，并对相位噪声的指标分配进行了论证，最后给出了输出频率范围为200MHz-1．25GHz的时钟电路的设计方案。通过实验验证，证明了上述分析的正确性。

Aiming at the needs for high precision and wideband dock circuit of an arbitrary waveform senerator, a method of generating variable clock with DDS and PLL is put forward in this paper. The paper analyses the choices of the DDS＇s parameters and the PLL＇s multiple in detail, and demonstrates the phase noise allocation. Finally, it presents the design scheme of the variable clock circuit of 200MHz to 1.25GHz. The correctness of the above analysis has been proved through the experiments.