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一种嵌入式处理器Cache的可在线配置和低功耗设计

A design of online configurable and low power cache for embedded processor
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摘要 本文提出了一种基于"组拼合"技术的嵌入式片上高速缓存(Cache)在线可配置结构。在线可配置Cache可以针对不同的应用,配置Cache的组关联等参数,从而在保持应用性能基本不变的前提下,有效降低Cache的动态功耗。其中水平组拼合方式与Gated-Vdd技术配合使用,不仅可以有效降低动态功耗,而且可以降低超深亚微米工艺中不断凸现的静态漏电功耗。将该结构应用于32-bit嵌入式处理器CK510中,PowerStone测试基准中的一组应用测试表明,组拼合可在线配置Cache结构可以显著降低处理器功耗。 A way-associative recombination based online configurable cache architecture is presented in this paper. The associative ways of cache can be configured according to applications features for reducing the dynamic power. There are two means to recombine the cache associative ways： horizontal concatenating and vertical concatenating. And the horizontal concatenating method coordinated with Gated-Vdd technique can not only reduce dynamic power, but also reduce static power, which accounts for 26% power consumption in 0.13 μm manufacture process. PowerStone benchmark results show online configurable cache can reduce power consumption dramatically.
作者 刘坤杰 孟建熠 严晓浪 葛海通
机构地区 浙江大学超大规模集成电路设计研究所
出处 《电路与系统学报》 CSCD 北大核心 2009年第5期37-41,共5页 Journal of Circuits and Systems
基金 国家"863"高科技研究发展计划资助项目(2004AA1Z1020)
关键词 嵌入式处理器 片上缓存 可配置设计:低功耗 embedded processor cache configurable design low power
分类号 TP303 [自动化与计算机技术—计算机系统结构]
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参考文献10

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二级参考文献17

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电路与系统学报
2009年 第5期

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