VLSI随机工艺变化下互连线建模与延迟分析

Modeling of interconnects and delay analysis in the presence of Random VLSI process variations

目前互连线的工艺变化问题已成为影响超大规模集成电路性能的重要因素。考虑了互连线工艺变化的空间相关性,将工艺参数变化建模为具有自相关性的随机过程,采用数值仿真及拟合方法得到寄生参数的近似表达式,最后基于Elmore延迟度量分析了随机工艺变化对互连延迟的影响,提出了工艺变化下互连延迟统计特性的估算方法,并通过仿真实验对方法的有效性进行了验证。

Interconnect process variations have become an important factor which affects the performance of very large scale integrated circuits. Considering the spatial correlation of interconnect process variations, they are modeled as stochastic processes with self-correlations. The approximate expressions of paracitic parameters are obtained by numerical simulations and fitting method. Finally, on the basis of Elmore delay metric the impact of random processes variations on interconnect delay is analyzed, and the method to estimate the statistical characterizations of interconnect delay in the presence of process variations is presented. The simulation experiments are provided to demonstrate the effectivity of the proposed method.