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一种基于标准逻辑单元的GALS异步封装电路 被引量：2

An asynchronous GALS wrapper based on standard logic cell
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摘要 基于点对点GALS模型,给出了异步封装电路的信号状态转换图(STG),基于Petrify设计了一种基于标准逻辑单元的GALS异步封装电路,包括同步/异步接口电路、具有分频及暂停功能的局部时钟等设计。由于所设计的异步封装电路具有不存在延时器件、没有使用特殊的异步逻辑单元等特点,所以论文基于两个同步计数器实现了GALS点对点模型进行仿真和FPGA验证,结果显示了整个异步封装及其GALS系统性能的正确性。 Based on the point to point GALS model, the signal transition graph of the asynchronous wrapper is presented. A novel asynchronous wrapper for GALS systems is presented in Petrify based on the standard logic cell. The synchronous and asynchronous interface circuits, local clock circuits with frequency dividing and pause function are included in the wrapper. Because the wrapper does not include delay device and special asynchronous elements, the GALS system with the asynchronous wrapper can be verified directly in FPGA based on two synchronous counters. The simulating and verifying results for point to point GALS model show that the asynchronous GALS wrapper can operate accurately.
作者 周端 朱樟明 杨银堂 史明华 梁政
机构地区 西安电子科技大学计算机学院 西安电子科技大学微电子研究所 芬兰Turku计算机科学研究中心
出处 《电路与系统学报》 CSCD 北大核心 2009年第5期112-116,共5页 Journal of Circuits and Systems
基金 国家自然科学基金资助项目(60725415 60676009)
关键词 全局异步局部同步 异步封装 信号转换 标准逻辑单元 FPGA globally asynchronous locally synchronous asynchronous wrapper signal transition standard logic cell FPGA
分类号 TN402 [电子电信—微电子学与固体电子学]
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参考文献7

  • 1Zhuang Shengxian, Li Weidong, Carlsson J. An asynchronous wrapper with novel handshake circuits for GALS systems [A]. IEEE Proc. on communications, circuits and systems 2002 [C]. 2002, 2: 1521-1525.
  • 2Christian Stahl, Wolfgang Reisig. Hazard in a GALS Wrapper: a Case Study [A]. Proc. 5^th Int. Conf. on Application of Concurrency to System Design (ACSD'05) [C]. 2005.
  • 3Jens Sparso, Steve Furbar. Principles of Asynchronous circuits Design-A Systems Perspective [M]. Kluwer Academic Publishers, 2002-09.
  • 4Gurkaynak F K, Villiger T, Oetiker S. An Introduction to the GALS Methodology at ETH Zurich [A]. CANDE (Computer-Aided Network DEsign) Workshop [C].Anchorage, Alaska, 2002.
  • 5Cortadella J, Kishinevsky M, Kondratyev A, Lavagno L. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers [J]. IEICE Transactions on Information and Systems, 1997, E80-D(3): 315-325.
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同被引文献18

  • 1吴继华,王诚.AheraFPGA/CPLD设计(高级篇)[M].北京:人民邮电出版社,2007.
  • 2CHAPIRO D M. Globally-asynchronous Locally-synchronous Systems[D]. Stanford.. Stanford Univ, CA Dept of Computer Science, 1984.
  • 3BEIGNE E, CLERMIDY F, LHERMET H, et al. An asynchronous power aware and adaptive NoC based circuit[J]. IEEE J of Solid-State Circuits, 2009,44 (4) : 1167--1177.
  • 4MUTTERSBACH J, VILLIGER T, FICHTNER W. Practical design of globally asynchronous locally-syn- chronous systems[C]//Asynehronous Circuits and Systems, Eilat: IEEE,2000:52--59.
  • 5GINOSAR R. Fourteen ways to fool your synchronizer [C]//Asynchronous Circuits and Systems, Vancouver: IEEE, 2003 : 89-- 86.
  • 6BEIGNE E, VIVET P. Design of on-chip and off chip interfaces for a GALS NoC architecture [C]//Asynehronous Circuits and Systems, Grenoble: IEEE, 2006 : 174--183.
  • 7SPARSO J, FURBER S. Principles of Asynchronous Circuit Design A System Perspective [ M ]. Norwell, MA : Kluwer, 2001.
  • 8QUINTON B R, GREENSTREET M R, WILTON S J E. Practical asynchronous interconnect network design[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2008,16(5) :579--588.
  • 9GAGNE R, BELZILE J, THIBEAULT G. Asynchronous component implementation methodology for GALS design in FPGAs[C]//Cireuits and Systems and TAISA Conference, Toulouse : IEEE, 2009 :1 -- 4.
  • 10DOBKIN R, GINOSAR R, KOLODNY A. Fast asynchronous shift register for bit-serial communication [C]//Asynchronous Circuits and Systems, Grenoble: IEEE,2006 : 118- 127.

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电路与系统学报
2009年 第5期

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