高速多芯片组件的互连延迟

Interconnection Delay in High-speed Multichip Modules

高速、高性能MCM中，往往把电路设计在欠阻尼小振荡输出的工作状态，以保持信号在互连传输线中的快速和平稳传播。已有文献关于互连延迟的研究往往是针对过阻尼或欠阻尼大振荡工作状态，即对应于通常的IC和PCB互连。即使对高速VLSI互连延迟的研究，考虑到计算的复杂性和有效性，也往往只处理过阻尼和欠阻尼大振荡两种状态，因此给出的结果如果用于研究MCM互连延迟，误差相当大甚至无效，文中讨论了一种研究MCM互连延迟的方法，并给出了延迟在三种工作状态下与各物理参数之间的确定关系式。

In high-speed, high-performance design of a Multi Chip Module(MCM),it is often to reach an underdamped state in a small oscillation to result infast and stable signal propagation. Many papers have been published on the study ofinterconnection delay. In most cases, however, the interconnection delay has beenanalyzed by using overdamped state or underdamped state in a large oscillation output. It corresponds to interconnection levels on a Printed Circuit Board (PCB) andlarge scale integrated circuit. And the interconnection delay for high-speed LSI hasalso been analyzed in the same way because of a reasonable compromise between accuracy and speed. If using this way to study interconnection delay in MCM, therewould be large error or inefficient. This paper presents a formal analysis of the interconnection delay in MCM circuits. Depending upon the circuit parameters,three delay formulas are respectively derived for the three delay domains.