基于FPGA的扩频信号快速捕获电路设计与实现

The Design and Realization of Spread Signal Acquisition Loop Based on FPGA

针对扩频通信中长伪码序列的快速捕获问题,文中提出了一种基于FPGA的扩频信号快速捕获方法,来解决低信噪比条件下长伪码序列的捕获问题。该方法采用伪码100支路并行捕获的方案,从而大大减少的捕获所需的时间,有效地改善了系统的性能。同时,在Altera公司的Quartus Ⅱ软件中,使用硬件描述语言VHDL和原理图相结合的方法进行了电路的设计实现。最后,把电路下载到Altera公司的Stratix EP1S80B956C6芯片中完成调试,测试结果表明该方法具有较快的捕获速度和较好的捕获性能。

Focused on the fast acquisition problem of long code sequence in spread communication system, a rapid acqui- sition method based on FPGA was proposed. The parallel acquisition of 100 branches was adopted, which greatly reduced the acquisition time of the PN code and improved the performance of acquisition effectively. At the same time, the hardware description language VHDL and the principle diagram were used to design the circuit in Altera＇s Quartus II software. At last, the software was downloaded to EP1S80B956C6. The experimental results show that the method is featured with fast acquisition speed and better performance.