摘要
提出一种新的基于FPGA的高斯白噪声生成器的设计和实现方法,给出设计的总体框图和分模块设计中的一些要点,阐述了主要部分的原理和电路实现方法。这种高斯噪声生成器与传统数字电路所组成的噪声生成器相比,通过利用QuartusⅡ中的一些既有功能电路(PLL),大大降低了设计的难度,提高了电路调试的灵活性,可用于多种环境下的通信系统性能分析与测试。
A new method is proposed for designing and implementing additive Gaussian white noise generator based on FPGA. In addition, there is a system block diagram and some key points in the module designing. Comparing with the traditional noise generator,this kind of Gaussine noise generator by using some given circuits such as PLL circuits from the Quartus Ⅱ software to reduce the design difficulty,thus improving the flexibility of circuit debugging, and it can be used in the performance analyzing and testing of communication system under many circumstances.
出处
《现代电子技术》
2009年第21期112-114,共3页
Modern Electronics Technique
基金
河南省教育厅自然科学研究指导计划项目(2008B510010)
郑州市科技攻关计划项目(083SGYG24123-2)
关键词
加性高斯白噪声
PN序列
前仿真
后仿真
additive Gaussine white noise
PN sequence
pre - simulation
post - simulation