FPGA开发中按键消抖与单脉冲发生器电路

Elimination Buffeting of Keystroke and Single Pulse Generator Circuit in FPGA Development Process

在介绍FPGA开发中按键消抖电路和单脉冲发生器电路原理的基础上,设计实现了键控单脉冲发生器,利用计数器解决了按键高频消抖问题,并通过按键产生与时钟脉冲完全相同的单脉冲。该单脉冲键控发生器可独立应用于其他FPGA电路设计中。在Quartus环境下给出Verilog HDL语言的行为及描述,并进行仿真实验,结果显示该电路合理可行。

The circuit principle of elimination buffeting of keystroke and a single pulse generator in FPGA development are introduced,and keying single pulse generator is achieved. It solves eliminating high - frequency buffeting problem by a counter and produces the single pulse which has the same pulse width and same phase with clock cycle. Keying a single pulse generator can be applied to other independent FPGA design. The behavior and description based on Verilog HDL language are given and it is simulated in Quartus software, the method is proved logical and feasible as a result.