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VCPPS:一种面向并行Verilog模拟的代码分割器

VCPPS:a Code Partitioner for Parallel Verilog Simulation
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摘要 本文介绍了一种面向并行模拟的Verilog代码分割器VCPPS。VCPPS通过图形化的方式进行人机交互,并采取用户启发式的方法指导分割。文章介绍了VCPPS设计与实现中的一些关键技术,通过分析可以看出,VCPPS可以正确地完成繁琐的Verilog代码分割工作,为并行Verilog模拟提供支持。 This paper presents VCPPS, a code partitioner for parallel Verilog simulation. In VCPPS, we provide a graphic user interface, and adopt a user heuristic approach in the partitioning process. Some key techniques of VCPPS are introduced in detail in this paper. Analysis has shown that VCPPS is suitable for the partitioning problem for parallel Verilog Simulation.
作者 张昆 钱磊 李宏亮 谢向辉
机构地区 江南计算技术研究所
出处 《计算机工程与科学》 CSCD 北大核心 2009年第A01期319-323,共5页 Computer Engineering & Science
基金 国家973计划资助项目(2007CB310907) 国家863计划资助项目(2007AA01Z117)
关键词 并行Verilog模拟 代码分割 parallel Verilog simulation code partitioning
分类号 TP391 [自动化与计算机技术—计算机应用技术]
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参考文献13

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二级参考文献18

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计算机工程与科学
2009年 第A01期

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