摘要
DRAM row buffer conflicts can increase memory access latency significantly. This paper presents a new pageallocation-based optimization that works seamlessly together with some existing hardware and software optimizations to eliminate significantly more row buffer conflicts. Validation in simulation using a set of selected scientific and engineering benchmarks against a few representative memory controller optimizations shows that our method can reduce row buffer miss rates by up to 76% （with an average of 37.4%）. This reduction in row buffer miss rates will be translated into performance speedups by up to 15% （with an average of 5%）.
DRAM row buffer conflicts can increase memory access latency significantly. This paper presents a new pageallocation-based optimization that works seamlessly together with some existing hardware and software optimizations to eliminate significantly more row buffer conflicts. Validation in simulation using a set of selected scientific and engineering benchmarks against a few representative memory controller optimizations shows that our method can reduce row buffer miss rates by up to 76% （with an average of 37.4%）. This reduction in row buffer miss rates will be translated into performance speedups by up to 15% （with an average of 5%）.
基金
Supported by the National Basic Research 973 Program of China under Grant No. 2005CB321602
the National Natural Science Foundation of China under Grant No. 60736012
