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基于时序重构的时序调整软件HTC的设计与实现

DESIGN AND IMPLEMENTATION OF THE SOFTWARE HTC FOR TIMING CORRECTION BASED ON RETIMING
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摘要 高层次综合是近年来电子设计自动化(EDA)领域中快速发展的一种技术,时序重构是高层次综合后端一种重要优化方法.文中介绍了基于时序重构的时序调整软件HTC的设计与实现,提出了时序调整软件HTC中的主要优化算法,此算法与以前严格优化的计算时间复杂性较高的时序重构算法比较,是一种计算时间复杂性为线性的近似优化算法.最后给出了时序调整软件HTC的电路实例测试结果,并与商用Synopsys公司的BRT(behavioralretiming)工具进行了比较,结果表明时序调整软件HTC与上述BRT工具的优化结果相同. High level synthesis and RTL synthesis are rapidly developed technologies in electronic design automation (EDA), and retiming is an important method for optimizing design in the back of RTL synthesis. Design and implementation of the software HTC for timing correction based on retiming are introduced in the paper , and some novel algorithms are proposed. These algorithms are approximately optimal methods based on retiming and linear computing complexity, compared with the original retiming algorithm which is optimal and of high computing complexity. The software HTC is tested with a lot of examples and compared with BRT(behavioral retiming) in behavioral compiler of Synopsys, and it is shown that the two tools can achieve the same optimal goal.
出处 《计算机研究与发展》 EI CSCD 北大核心 1998年第11期1048-1052,共5页 Journal of Computer Research and Development
关键词 同步时序电路 时序调整软件 EDA 设计 synchronous circuits, high level synthesis, retiming Class number TP29
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参考文献2

  • 1Zheng Yan,Proc of 4th Int Conf on Solid-State and IC Technology,1995年,631页
  • 2王进祥,微电子学与计算机,1995年,12卷,增刊,149页

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