使用扩展逻辑效力的逻辑路径尺寸优化方法

Logic Path Sizing Optimization Using Extended Logical Effort

为解决集成电路物理设计中考虑互连线影响的逻辑路径延迟优化问题,提出一个计入互连线负载的扩展的逻辑效力(ELE),并针对ELE给出一个可同时优化逻辑路径中各个逻辑门尺寸及各段互连线长度的优化流程.ELE在保留原有逻辑效力参数的同时,使用互连寄生参数提取软件获得的Π型互连线参数,实现对带有互连线负载的逻辑门的传播延迟的描述和估计;逻辑路径优化流程采用效力延迟分配策略作为初始条件来表示各段互连线负载对总效力延迟的影响,将所用目标单元库和制造工艺的物理尺寸信息作为限制条件,以ELE表达式为核心展开优化计算,辅以动态规划办法,无需迭代运算,仅通过一轮计算即可求得全部结果.实验结果表明,该流程计算任务简单,资源耗费少,可以准确、快速地获得所需的逻辑门尺寸和互连线长度;结果清晰合理,与目标单元库和工艺库完全兼容.

Path delay optimization in awareness of interconnect wire has become an important issue in VLSI physical design process. An Extended Logical Effort （ELE） that characterizes total delay of logical gate and interconnect wire load, as well as an ELE based path sizing optimization flow, are proposed. Parameters from LE are maintained in ELE and interconnect parameters are fully supported by back-end RC extraction flow. Given delay distribution strategy parameters and total effort delay value, this optimization flow can generate both optimal logical gate sizes and interconnect wire lengths in just one calculation pass without iteration. Dynamic programming is used to limit the solutions of every stage to those that satisfy both physical and technology constraints. Compared with the existing method, the proposed flow meets various target delay requirements, and results in shorter total wire length and smaller area with fewer computing resources.