基于DS-CDMA系统的PDA+LDPC双迭代接收机

PDA+LDPC Doubly-Iterative Receiver Based on DS-CDMA Systems

本文针对DS-CDMA系统来给出PDA+LDPC双迭代接收机,该双迭代接收机由随机数据联合检测检测器(PDA)和LDPC译码器级联而成。PDA检测器可与LDPC译码器通过外迭代运算交互信息来提高系统性能。LDPC译码器由变量节点译码器(VND)和校验节点译码器(CND)组成,在每一次外迭代运算过程中,VND与CND通过一定次数的内迭代运算来交互信息。本文考虑当总的LDPC迭代译码次数一定时,选择不同的外迭代运算次数和内迭代运算次数对系统性能的影响,研究结果表明,当多址干扰量较小时,减少内迭代运算次数(增大外迭代运算次数)可获得较好的系统性能;而当多址干扰量较大时,适当增加内迭代运算次数(减小外迭代运算次数)可获得更好的系统性能。

This paper presents the PDA＋LDPC doubly-iterative receiver for the DS-CDMA systems. The proposed doubly-iterative receiver is constituted by the Probabilistie Data Association Detector （PDA） and the LDPC decoder. PDA detector and LDPC decoder can exchange information through outer loop to improve the performance of the system. The LDPC decoder is made up by the Variable Node Decoder （VND） and Check Node Decoder （CND）. During each outer loop, VND and CND can exchange information through some number of inner loops. This paper considers the performance of the systems by choosing different number of inner loops and outer loops on the condition of the total determined LDPC decoding iteration numbers. The research results demonstrate that when the Multi-user Access Interference（MAI） is less, better performance can be obtained by decreasing the number of inner loops （increasing the number of outer loops）; conversely, properly increasing the number of inner loops （decreasing the number of outer loops） can achieve some performance gains.