摘要
The current network-on-chip （NoC） topology cannot predict subsequent switch node status promptly. Switch nodes have to perform various functions such as routing decision, data forwarding, packet buffering, congestion control and properties of an NoC system. Therefore, these make switch architecture far more complex. This article puts forward a separating on-chip network architecture based on Mesh （S-Mesh）, S-Mesh is an on-chip network that separates routing decision flow from the switches. It consists of two types of networks： datapath network （DN） and control network （CN）. The CN establishes data paths for data transferring in DN. Meanwhile, the CN also transfers instructions between different resources. This property makes switch architecture simple, and eliminates conflicts in network interface units between the resource and switch. Compared with 2D-Mesh, Toms Mesh, Fat-tree and Butterfly, the average packet latency in S-Mesh is the shortest when the packet length is more than 53 B. Compared with 2D-Mesh, the areas savings of S-Mesh is about 3%-7/% and the power dissipation is decreased by approximate 2%.
The current network-on-chip （NoC） topology cannot predict subsequent switch node status promptly. Switch nodes have to perform various functions such as routing decision, data forwarding, packet buffering, congestion control and properties of an NoC system. Therefore, these make switch architecture far more complex. This article puts forward a separating on-chip network architecture based on Mesh （S-Mesh）, S-Mesh is an on-chip network that separates routing decision flow from the switches. It consists of two types of networks： datapath network （DN） and control network （CN）. The CN establishes data paths for data transferring in DN. Meanwhile, the CN also transfers instructions between different resources. This property makes switch architecture simple, and eliminates conflicts in network interface units between the resource and switch. Compared with 2D-Mesh, Toms Mesh, Fat-tree and Butterfly, the average packet latency in S-Mesh is the shortest when the packet length is more than 53 B. Compared with 2D-Mesh, the areas savings of S-Mesh is about 3%-7/% and the power dissipation is decreased by approximate 2%.
基金
sponsored by the Hi-Tech Research and Development Program of China (2009AA01Z105)
the Research Foundation of the Ministry of Education of China, and the Intel Information Technique (MOE-INTEL-08-05)
