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物理可观测下DES的安全性研究 被引量:7

Research on the DES Physical Observable Security
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摘要 利用物理观测效应进行的旁路攻击,是通过对密码设备工作时泄漏的时间、功耗等信息的分析,获取密码系统的密钥或相关秘密信息.已有大量防护对策但并没有从根本上阻止攻击.本文在AT89C52上加载了DES算法,并在该平台上对差分功耗旁路攻击与防护方法进行了实验和验证.根据Micali和Reyzin建立的物理观测密码术理论模型,将该模型具体化,对可以抵抗黑盒攻击的密码要素进行修正以抵抗基于物理泄漏的旁路攻击,将RO(random ora-cle)模型用于物理观测现实世界的安全性证明,给出了对称加密方案物理可观测下安全性定义,并对DES定义了在DPA攻击下的安全性. The security of cryptographic implementations with respect to "physical observation attacks" named side-channel attacks, in which adversaries are enhanced with the possibility to exploit physical leakages such as power consumption or electromagnetic radiatiou. A lot of countermeasures have been experimented, but do not fundarnentally prevent them.In this paper,DES is implemented on AT89C52.DPA and countermeasure experiments have been done on this platform.Physically Observable cryptography is built by Micali and Reyzin who initiated a theoretical analysis of side-channels. Our work is to apply the "Physical-Observation" attacks to practice for Symmetric Encryption schemes and find out how it is applied to DES-DPA attack practice for Symmetric Encryption schemes with random oracle model.
出处 《电子学报》 EI CAS CSCD 北大核心 2009年第11期2389-2395,共7页 Acta Electronica Sinica
基金 国家自然科学基金(No.60571037) 国家863高技术研究发展计划(No.2007AA01Z454)
关键词 数据加密标准 差分功耗分析 随机预言模型 可证安全 旁路分析(侧信道分析) 物理观测密码术 data encryption standard (DES) differential power analysis (DPA) random oracle model provable security side-channel analysis physical observable cryptography
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参考文献16

  • 1M L Akkar, C Girand. An implementation of DES and AES secure against some attacks[A]. Cryptographic Hardware Embedded System-CHES 2001 [C]. Paris: Springer-Verlag, 2001. 309 - 318.
  • 2J A Fournier, S Moore,H Li,R D MuUins,G. S Taylor. Security evaluation of asynchronous circuits[ A]. Cryptographic Hard- ware Embedded System-CHES 2003[ C]. Cologne: Springer- Verlag,2003. 137 - 151.
  • 3S Mangard. Hardware countermeasures against DPA-a statistical analysis of their effectiveness [ A ]. CT-RSA 2004 [ C ]. San Francisco: Springer-Verlag, 2004. 222 - 235.
  • 4李翔宇,孙义和.采用数据流模式提高乱序执行密码芯片的安全性[J].电子学报,2007,35(2):202-206. 被引量:2
  • 5G Yeap. Practical Low Power Digital VLSI Design[M]. USA: Kluwer Academic Publishers, 1998.
  • 6E Brier, C Clavier, F Olivier. Correlation power analysis with a leakage model [ A ]. Cryptographic Hardware Embedded System-CHES 2004[ C]. Boston: Springer-Verlag, 2004.16 - 29.
  • 7Federal Information Processing Standards Publication 46- 3 (FIPS PUB 46 - 3) : Data Encryption Standard[S].
  • 8T S Messerges,E A Dabbish,R H Sloan. Examining smartcard security under the threat of power analysis attacks [J]. IEEE Transactions on Computers,2002,51 (5):541 -552.
  • 9S Micali, L Reyzin. Physically observable cryptography (extended abstract) [A]. 1st Theory of Cryptography Conference [C]. Cambridge, MA: Springer-Verlag, 2004.278 - 296.
  • 10A W Dent, J MaloneLee. The physically observable security of signature schemes [A]. Cryptography and Coding: 10th IMA International Conference [ C ]. Cirencester, UK: Springer-Verlag, 2005.220 - 232.

二级参考文献16

  • 1李翔宇,孙义和.用于密码芯片抗功耗攻击的功耗平衡加法器[J].Journal of Semiconductors,2005,26(8):1629-1634. 被引量:3
  • 2Irwin J, et al. Instruction stream mutation for non-detemninistic processors[ A ]. Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors[ C].San Jose,CA, USA: IEEE. Comput Soc,2002.286- 295.
  • 3May D,et al. Random register renaming to foil DPA[ A] .Koc C K, et al. Cryptographic Hardware and Embedded Systems-CHES 2001. Third Intemational Workshop. Proceedings [ C ].Paris, France: Springer-Vedag, 2001.28 - 38.
  • 4Tiri K,et al.A VLSI design flow for secure side-channel attack resistant ICs[ A ]. Proceedings. Design, Automation and Test in Europe[ C]. Munich, Germany: IEEE Comput Soc, 2005.58 -63.
  • 5Tiff K, et al. A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation[ A]. Proceedings Design, Automation and Test in Europe Conference and Exhibition[ C]. Paris,France: IEEE Comput Soc,2004.246- 251.
  • 6Sokolov D, et al. Improving the security of dual-rail circuits [A ]. Joye M, et al. Ctyptographic Hardware and Systems-CHES 21304.6th International Workshop. Proceedings [ C ]. Cambridge, MA, USA: Springer- Verlag, 2004.282 - 297.
  • 7Jordan H f, et al.Fundamentals of Parallel Processing[M].北京:清华大学出版社,2003,292—318.
  • 8JoanD,等.高级加密标准(AES)算法——Rijndael的设计[M].北京:清华大学出版社,2003:31—64.
  • 9Jens S, et al. Principles of Asynchronous Circuit Design: A Systems Perspective [ M]. Boston: Kluwer Academic Publishers,2001:9-40.
  • 10Moore S,et al.Improving smart card security using self-timed circuits[ A ~. Proceedings Eighth International Symposium on Asynchronous Circuits and Systems [ C ]. Manchester, UK:IEEE. Comput Soc,2002.211 - 218.

共引文献1

同被引文献57

  • 1丁文霞,卢焕章,谢剑斌,王浩.基于混沌系统的独立密钥DES数字图像加密算法[J].计算机应用研究,2006,23(2):113-115. 被引量:7
  • 2倪皖荪,华一满,邓浩,覃团发.混沌通讯[J].物理学进展,1996,16(3):645-656. 被引量:19
  • 3高娜娜,李占才,王沁.一种可重构体系结构用于高速实现DES、3DES和AES[J].电子学报,2006,34(8):1386-1390. 被引量:19
  • 4赵佳,曾晓洋,韩军,陈俊.简化的抗零值功耗分析的AES算法及其VLSI实现[J].计算机工程,2007,33(16):220-222. 被引量:1
  • 5P. Kocher, J. Jaffe, B. Jun. Differential power analysis[ A]. Ad vances in Cryptology-CRYPTO' 99: 19th Annual International Cryptology Conference [ C ]. Santa Barbara, CA, USA: Springer-Verlag, 1999.388 - 397.
  • 6F-X Standaert,S B Ors,B Preneel Power analysis of an FPGA implementation of Rijindael: Is pipelining a DPA countermea sure? [ A]. Cryptographic Hardware Embedded System-CHES 20041[ C]. Boston: SpfingerVerlag, 2004.30 - 44.
  • 7S Mangard, N Pramstaller, E Oswald. Successfully attacking masked AES hardware implementations [ A ]. Cryptographic Hardware Embedded System-CHES 2005[ C]. Edinburgh, UK: Springer-Verlag, 2005. 157 - 171.
  • 80 Kommerling,M G Kuhn. Design principles for tamper-resis- tant smartcard processor [A ]. The USENIX Workshop on Smartcard Technology Smartcard 1999 [ C ]. Chicago: USENIX Association, 1999.9 - 20.
  • 9K Tiff, M Akmal, I Verbauwhede. A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards[A]. Euro pean Solid-State Circuit Conference-ESSCIRC 2002[ C]. Firenze, Italy: University of Bologna, 2002.403 - 406.
  • 10K Tiri, I Verbauwhede. A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation[ A ]. De sign, Automation, and Test in Europe Conference-DATE 21304 [ C] .Paris,France: IEEE Computer Society,2004.246- 251.

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