∑-△DAC中多级插值滤波器的研究与设计

Research and Design of Interpolation Filter for ∑-△DAC

设计了一种用于数字语音处理的插值滤波器。该滤波器利用多项插值原理,对采样率为44.1kHz,分辨率为16bit的输入音频信号(PCM码)进行128倍过采样。在Matlab下完成系统仿真后,采用Verilog对滤波器进行功能描述,并利用ModelSim工具进行仿真。仿真结果表明能够满足设计性能要求。

This paper presents an efficient way to implement an interpolation filter for digital signal process.The filter based on multiterm interpolation principle,over-samples（128×）the audio signal（PCM code）with the sample rate of 44.1 kHz and the resolution of 16 bit.After simulated system in the Matlab,the filter was implemented with VerilogHDL,simulated and synthesized with ModelSim EDA tools.The simulation result illustrates that the design gives out a performance satisfactorily.