一种开环高速高精度采样保持电路

A High-Speed High-Precision Open-Loop of Sample-and-Hold Circuit

设计了一种改进型开环结构采样保持电路。与传统Miller电容开环结构相比,本设计采用了新型Bootstrapped开关,不但实现了沟道导通电阻线性化,而且消除了与输入信号相关的时钟馈通;采用全差分结构消除了共模信号引入的误差以及偶阶谐波,提高了电路的信噪比;采用高速高精度缓冲器增大电路的驱动能力,实现了高速高精度采样。设计采用0.35μm n-well CMOS工艺,经仿真验证,在驱动2.5pF负载电容下采样率达到100MSPS,电路有效位数12bits,功耗为21.5mW。

In this paper,a modified open-loop sampleand-hold circuit,realized in a standard 0.35μm n-well CMOS process,is present.Unlike the traditional Miller capacitor open-loop structure,a developed bootstrapped switch is adopted in this design,which not only obtains the linear channel resistor but also eliminates the clock feed through associated with the input signal.The full difference structure is adopted aiming to eliminate the error and the even-orders harmonic coming from the common signal,and the SNR value is increased. The driving force is improved because of using the high speed high precision buffer. The high speed high precision is realized based on the above technologies. The sample rate is higher than 100MHz per second with the load capacitor 2.5pF and the resolution is 12 bits. The power consumption is 21.5mW.