4个加数的并行加法器及扩展接口的研究

Research on a parallel adder with 4 binary addends and its interface

算术逻辑运算单元(ALU)决定着中央处理器(CPU)的性能,而加法器又决定着ALU的性能。为了提高CPU的性能,文章提出了一种4个加数的并行加法器及其接口扩展的研究方案,论述了所提新型加法器的工作原理和过程,同时描述了接口扩充思想;最后,采用MAX+PLUSⅡ对设计电路进行了模拟验证,实验结果说明了所提加法器的设计合理性。

The arithmetic logic unit（ALU） decides the performance of the Central Processing Unit （CPU）, while the adder decides that of the ALU. To improve the performance of the CPU, a parallel adder with 4 binary addends and its interface are proposed. The working principle and process of the novel adder are discussed, and its interface extension is described. Finally,the MAX＋PLUS Ⅱ is adopted to simulate and validate the proposed adder. Experimental results indicate that the proposed design scheme is not only reasonable, but it can also calculate 4 binary addends faster than a carry look-ahead adder using the serial adding scheme.