Integrated power electronics module based on chip scale packaged power devices

基于芯片尺寸封装功率器件的集成电力电子模块(英文)

High performance can be obtained for the integrated power electronics module（IPEM） by using a three-dimensional packaging structure instead of a planar structure. A three- dimensional packaged half bridge-IPEM （HB-IPEM）, consisting of two chip scale packaged MOSFETs and the corresponding gate driver and protection circuits, is fabricated at the laboratory. The reliability of the IPEM is controlled from the shape design of solder joints and the control of assembly process parameters. The parasitic parameters are extracted using Agilent 4395A impedance analyzer for building the parasitic parameter model of the HB- IPEM. A 12 V/3 A output synchronous rectifier Buck converter using the HB-IPEM is built to test the electrical performance of the HB-IPEM. Low voltage spikes on two MOSFETs illustrate that the three-dimensional package of the HB-IPEM can decrease parasitic inductance. Temperature distribution simulation results of the HB-IPEM using FLOTHERM are given. Heat dissipation of the solder joints makes the peak junction temperature of the chip drop obviously. The package realizes three-dimensional heat dissipation and has better thermal management.

采用三维封装结构取代传统的平面封装结构可获得高性能集成电力电子模块.在实验室完成由2只芯片尺寸封装MOSFET和驱动、保护等电路构成的三维封装半桥IPEM.从互连焊点形状的优化和封装工艺过程参数的控制出发,进行IPEM的可靠性控制.采用阻抗分析仪Agilent 4395A测量IPEM的寄生参数,建立了半桥IPEM的寄生参数模型;采用半桥IPEM构成12V/3A输出的同步整流Buck变换器,2只MOSFET的漏源极尖峰电压小,说明HB-IPEM的三维封装结构有效减小了寄生电感.运用Flotherm软件对半桥IPEM进行了热分析,给出了温度分布仿真结果.焊料凸点传热使芯片的最高结温明显降低,三维封装结构实现了良好的热设计.