基于存储队列的Cache访问性能优化研究

Research on High-performance Cache Accessing Based on Load Store Queue

高性能处理器普遍采用片上集成大容量复杂结构的一级Cache提高处理器性能,但随着Cache容量和复杂度的增加,访问Cache所产生的访存延迟和功耗明显增加;基于存储队列,提出了一种通过减少Cache访问次数来降低功耗和延迟的方法,利用存储队列来缓存Load/Store指令的数据,并且当存储队列不满时,通过空闲入口暂存已经完成的仿存数据,提高了连续访存数据的复用率,减少了Cache的访问次数;仿真结果显示,该方法在增加少量的控制逻辑基础上,显著减少了Cache的访问次数,降低了Cache的功耗,减少了访存延迟,加快了执行速度。

High--performance processors use a large set-associative L1 Data Cache in order to increase performance. The latency and power consumption of L1 Data Cache continues to grow with increasing Cache size and complexity. Based on load store queue, this paper proposes a method of reducing power consumption and delay by reducing the number of Cache accessed. Data values on both loads and stores are stored in the load store queue. When the queue is not full, it caches previously accessed data values on both loads and stores in unused entries after the corresponding memory access instructions have been committed, reducing the number of Cache accessed by reusing the data values when accessing Cache in series. The results indicate that the number of Cache accessed is reduced by adding a little hardware and control log- Lic, reducing the energy consumption of Cache and average accessed latency.