一种低功耗容错运动估计硬件结构

Low Power Error-Resilient Motion Estimation Architecture

提出一种低功耗的运动估计硬件结构。该结构在并行GEA结构的基础上,对关键的绝对差和模块应用了差错复原机制,以对抗在工艺参数波动和(或)工作电压超比例缩小(VOS)时可能产生的逻辑级时序错误。这里采用一个亚采样电路ISR-SSAD,将VOS技术和算法级容噪设计集成到绝对差和模块中,实现了该模块的差错检测和纠正,与原并行GEA结构相比,具有更低的功耗。计算结果表明,整个运动估计模块的功率可节省16%。

A new low - power motion estimation architecture is proposed. Based on the parallel GEA architecture, the proposed architecture employs the principle of error - resiliency to combat logic level timing errors. Referred to as Input Subsampied Replica SsAD （ISR- SSAD）,the proposed architecture incorporates an input subsampled replica of the Main Subsampled - Sum - of - Absolute -Difference （MSSAD） block for detecting and correcting errors in the MSAD block. The proposed architecture achieves power reduction compared to conventional parallel GEA architecture. Computations show that using typical parameter values,the total power savings of 16% can be achieved.