32×32高速乘法器的设计与实现

32×32 High-speed Multiplier Design and Implementation

设计并实现了一种32×32高速乘法器.本设计通过改进的基4Booth编码产生部分积,用一种改进的Wallace树结构压缩部分积,同时采用一种防止符号扩展的技术有效地减小了压缩结构的面积.整个设计采用Ver-ilog HDL进行了结构级描述,用SIMC0.18μm标准单元库进行逻辑综合.时间延迟为4.34ns,系统时钟频率可达230MHz.

A design of hign-performance 32 × 32 multiplier is presented. The design, which generates partial products by modified radix-4 Booth encoding, compresses them using a modified Wallace tree structure, and optimize the compressor structure by preventing sign-extend algorithm. The whole design is described in Verilog HDL at structure level, and synthesized using the SIMC 0.18/ma standard ceU library. The synthesis result of this design shows that the delay can be reduced to 4.34 ns and the frequency of the system can reach 230MHz.