摘要
提出了一种6个加数的并行加法器及其接口扩展的研究方案.论述了所提新型加法器的工作原理和过程,同时描述了接口扩充思想.最后,采用MAX+PLUSⅡ对设计电路进行了模拟验证.实验结果说明了所提加法器的设计合理性,也证明了该加法器对6个加数的计算比采用串行累加更快.
A parallel adder with 6 binary addends and its interface are proposed. Working principle and process of the novel adder are discussed, and its interface extension is described. Finally, MAX ＋ PLUS II is exploited to simulate and validate the proposed adder. Experimental results indicate that the proposed design scheme is not only reasonable, but also can faster calculate 6 binary addends than a carry look-ahead adder using the serial adding scheme.
出处
《微电子学与计算机》
CSCD
北大核心
2009年第12期27-30,共4页
Microelectronics & Computer
基金
安徽省高校省级自然科学研究资金项目(2006KJ042B)
