摘要
针对传统Viterbi译码方法硬件资源开销大、译码速度低的缺点提出了基于FPGA的卷积码分组译码方法。该方法将待译码数据分成若干组,充分考虑前后分组间的相互影响并分别进行译码,综合考虑每个分组的译码结果后得到最终的译码输出。研究表明:在相同的回溯深度下,该方法与传统的Viterbi译码方法相比,减少了硬件设计的逻辑门数量,提高了系统译码速度。
A packet decoding method for convolutional codes is proposed based on Field Programmable Gate Array（FPGA）.It overcomes the shortcomings of larger consumption of hardware and lower decoding speed with the traditional Viterbi method.By this method the data to be decoded are divided into several groups first,and the mutual influences among the groups are fully considered.Then the data of different groups are decoded respectively.The final decoding output is obtained after integrative consideration of the decoding results of each data group.Investigation shows that,with the same feedback depth,the proposed decoding method can save hardware consumption and increase the decoding speed in comparison with the traditional Viterbi decoding method.
出处
《吉林大学学报（工学版）》
EI
CAS
CSCD
北大核心
2009年第6期1668-1671,共4页
Journal of Jilin University:Engineering and Technology Edition
基金
总装备部预先研究项目
关键词
信息处理技术
FPGA
卷积码
分组译码
communication engineering
FPGA
convolutional code
packet decoding
