基于门控时钟的片上网络路由单元低功耗设计

Low-Power Design of Router for NoC With Clock Gating

NoC(Network-on-Chip)已经逐渐代替片上总线互连,成为片上系统的解决方案,然而迅速增长的功耗将阻碍NoC的性能与发展.从NoC的核心部件路由单元入手,在研究了二维Mesh下片上网络路由单元的结构和门控时钟技术的基础上,对路由单元功耗最集中的输入端口采用了模块级门控时钟技术进行低功耗设计,通过利用软件判断控制门控使能信号来实现受控端口时钟的通断.在ModelSim SE PLUS 6.0环境下进行路由单元功能仿真,并通过Synopsys公司的Design Compiler工具给出综合结果,路由单元工作频率200MHz,动态功耗51.0457mW,降低了11.38%.

Network-on-Chip （NoC） architectures are gradually replacing interconnection on chip, and thus becoming an attractive solution to address the inter-connect delay problems in System-on-Chip. However, increased power dissipation has hindered the wide-deployment of NoCs. From Router, the kernel unit, on the basis of the study of the structure of router on the bi-dimensional Mesh chip and the technique of clock gating, the paper proposes a low-power design of Router with Model level Clock gating （MCG） techniques, by using code to control the clock signal of the Input. Functional simulation is done with ModelSim SE PLUS 6. 0 tools. Results of synthesis with design compiler of the synopsys Inc. show that the dynamic power consumption of a router is reduced by 11.38% with 200 MHz operating frequency.