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改善系统能量效率的体系结构方法:并行处理 被引量：5

An Efficient Architecture Method for Improving Energy Efficiency:Parallel Processing
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摘要 因为对高性能微芯片和系统设计的广泛影响,能量消耗问题受到计算机界越来越广泛的关注.多个层次的技术被用于改善系统的能量效率,并行处理是体系结构层提高能量效率的主要手段.并行处理使用性能适中的计算节点减少能量消耗,使用多个节点并行执行维持高吞吐量.文中分析了并行处理提高能量效率的基本原理,给出了并行处理的时间开销和能量开销模型.基于模型分析,对低电压并行系统、动态电压调节(Dynamic Voltage Scaling,DVS)的并行系统和多核微处理器3个并行处理方向进行了展望,给出了这些并行处理方向改善能量效率的空间. Energy consumption has been paid increasing attention to in the computer domain because of its deep influence on the design of high performance chips and systems. Many techniques are proposed to improve energy efficiency of computer systems, and in the paper the author focuses on parallel processing on architecture level. Parallel processing improves energy efficiency by using some computing nodes with moderate performance, which maintain high throughput by parallel execution. In this paper, the authors present the fundamental of parallel processing improving energy efficiency, and models the time and energy overhead involved in parallel execution. Based on the models, the author investigates low voltage parallel systems, parallel systems with dynamic voltage scaling, and multi-core microprocessors, and reveals their potential of improving energy efficiency.
作者 易会战 刘永鹏
机构地区 国防科学技术大学计算机学院计算机研究所
出处 《计算机学报》 EI CSCD 北大核心 2009年第12期2475-2481,共7页 Chinese Journal of Computers
基金 国家自然科学基金"软件指导的高性能计算机系统功耗和热量管理"(60903059) 国家"八六三"高技术研究发展计划项目"面向片上多处理器系统的程序设计环境"(2008AA01Z110) 国家科技重大专项(2009ZX01036-001-003-001) 高效能服务器和存储技术国家重点实验室开放基金项目(2009 HSSA04)资助
关键词 并行处理 能量效率 动态电压调节 低电压设计 多核处理 parallel processing energy efficiency dynamic voltage scaling low-voltage design multi-core processing
分类号 TP311 [自动化与计算机技术—计算机软件与理论]
  • 相关文献

参考文献11

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同被引文献37

  • 1刘近光,梁满贵.多核多线程处理器的发展及其软件系统架构[J].微处理机,2007,28(1):1-3. 被引量：22
  • 2卢春鹏.动态电压与频率调节在降低功耗中的作用[J].单片机与嵌入式系统应用,2007,7(5):12-14. 被引量：11
  • 3REINDERS J. Intel threading building blocks: outfitting C++ for multi-core processor parallelism [M]. Sebastopol, CA, USA: O'Reilly Media, 2007: 133- 168.
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  • 5BIENIA C, KUMAR S, SINGH J P, et al. The PAR- SEC benchmark suite: characterization and architectural implications [C] // Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques. New York, USA: ACM, 2008: 72-81.
  • 6AGRAWAL K, LEISERSON C E, SUKHA J. Executing task graphs using Work-Stealing [C]//Proceedings of 24th IEEE International Parallel and Distributed Processing Symposium (IPDPS). Piscataway, NJ, USA: IEEE, 2010: 1-12.
  • 7AGRAWAL K, HE Y, LEISERSON C E. Adaptive work stealing with parallelism feedback [C]// Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). New York, USA:ACM, 2007: 112-120.
  • 8HILL M, MARTY M. Amdahl's law in the multicore era [J]. Computer, 2008, 41(7):33-38.
  • 9CHAPMAN B, HUANG Lei. Enhancing OpenMP and its implementation for programming multicore systems [M]//Parallel Computing: Architectures, Algorithms, and Applications. Amsterdam, Netherlands: IOS Press, 2008 : 3-18.
  • 10Choi K, Soma R, Pedram M. Dynamic Voltage and Frequency Scaling Based on Workload Decomposition[C]//Proc. of Inter- national Symposium on Low Power Electronics and Design. New York, USA: ACM Press, 2004: 174-179.

引证文献5

二级引证文献14

计算机学报
2009年 第12期

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