基于FPGA的异步FIFO缓存设计

Implementation of asynchronous FIFO buffer based on FPGA

介绍了异步FIFO的类型以及工作原理,研究了使用用FPGA芯片内部的双口RAM来实现异步FIFO设计方案,重点阐述了如何判断空/满标志信号以及消除亚稳态的设计思路。针对多位跨时钟域的数据传输,可能出现亚稳态导致数据出现不可知的错误,讨论了通过格雷码对读写地址进行编码以用来减少亚稳态出现的概率,并给出了具体的程序流程图,进行了仿真验证。这种方法设计的异步FIFO具有高速,高可靠性,移植性强的特点。

The article describes the types of asynchronous FIFO, as well as principle. It studies the scheme usage of the internal resources Dual-port RAM of FPGA implement asynchronous FIFO, focused on how to judge the empty/ full flag signals and reduce the probability of metastable . It may give rise to metastable which will cause unknown data when a number of data transfer from one clock to another clock. The code of read and write address are gray code , which can eliminate the metastahle. It realizes with the VHDL language, finally has carried on the simulation confirmation. This design is high-speed, high reliability, portability and strong features.